1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a pad polysilicon film for extracting source and drain electrodes or a nonvolatile semiconductor memory such as an EEPROM and a method of manufacturing the same.
2. Description of the Related Art
A technique of preventing an extraordinary resist pattern exposure due to the step between an element isolation region (field region) and an element formation region on forming a gate electrode wiring layer of a MOS transistor is disclosed in Japanese Patent Laid-Open No. 6-21054.
In the technique disclosed in Japanese Patent Laid-Open No. 6-21054, a first polysilicon film is formed on the entire surface of a silicon substrate having a field oxide film formed thereon. Thereafter, the first polysilicon film is polished to expose the field oxide film or leave the first polysilicon film having a predetermined thickness on the field oxide film, thereby planarizing the entire structure. When the first polysilicon film is polished to expose the field oxide film, a second polysilicon film is formed on the resultant structure, and a resist pattern is formed on the second polysilicon film. When the first polysilicon film having a predetermined thickness is left on the field oxide film, a resist pattern is formed on the planarize first polysilicon film. In any case, the resist pattern is formed across a field region and an active region (element formation region) surrounded by the field region. With this structure, an extraordinary resist pattern formation due to variations of the exposure focal position is prevented. Consequently, the width of the gate electrode wiring can be small-sized to almost the lowest exposure limit.
Japanese Patent Laid-Open No. 6-349826 discloses use of almost the same technique as that of Japanese Patent Laid-Open No. 6-21054, to flush gate electrode layer in the element formation region and gate wiring layer in the field region are formed to the same level, thereby preventing etching into the substrate upon etching the gate electrode wiring layer.
Japanese Patent Laid-Open No. 4-62874 discloses a technique of preventing a mask displacement in gate electrode formation process, in which a gate electrode is deposited on the entire surface of a semiconductor substrate including an element isolation oxide film with a gate oxide film intervened there between. The surface of the gate electrode is planarized to the surface of the element isolation oxide film, so that the gate electrode is buried between adjacent element isolation oxide films.
Japanese Patent Laid-Open Nos. 5-335586 and 5-129621 disclose a technique to improve information storage capability of a nonvolatile semiconductor device, in which a polysilicon film serving as a floating gate is deposited on the entire surface of a semiconductor substrate having a filed oxide film. The polysilicon film is surface-polished patterned into a floating gate having a predetermined shape.
Chemical mechanical polishing (CMP) as a polishing method is disclosed in Japanese Patent Laid-Open No. 62-102543 or 8-17831.
Japanese Patent Laid-Open No. 6-69352 discloses a technique in which gate electrodes formed on a gate oxide film are covered with an insulating film, a thick polysilicon film is formed to bury each gate electrode, and the surface of the polysilicon film is etched back to expose the upper surface of the insulating film which covers the gate electrodes. In this case, the polysilicon film is separated at a separation width equal to the width of the gate electrode upon etching back the polysilicon film, so that polysilicon pads (pad polysilicon films) are formed. More specifically, the polysilicon pads are formed such that the separation width between adjacent polysilicon pads equals the width of the gate electrode. For this reason, the width of the gate electrode can be small-sized to the lowest exposure limit.
A mask formation technique of forming a pattern having a width equal to or smaller than the exposure limit is disclosed in, e.g., Japanese Patent Laid-Open No. 1-114041. More specifically, a silicon oxide film is formed on a silicon substrate to be patterned, and a photoresist having a pattern with a width as small as the exposure limit is formed on the silicon oxide film. Subsequently, the silicon oxide film is anisotropically etched using the photoresist as a mask to form a silicon oxide film having the same width as that of the photoresist pattern. The silicon substrate is dipped in dilute hydrofluoric acid to make the width of the silicon oxide film smaller than the exposure limit, and the photoresist is removed. Thereafter, a new photoresist is formed to bury the silicon oxide film. Etching is performed to expose the upper surface of the silicon oxide film. The silicon substrate is dipped again in dilute hydrofluoric acid to remove the silicon oxide film. With these processes, a mask having a pattern with a separation width smaller than the exposure limit is complete.
Japanese Patent Laid-Open No. 8-70120 discloses a technique in which a stopper portion consisting of an oxide film which covers the upper and side surfaces of a gate electrode is formed, and an impurity diffusion region consisting of polysilicon is formed between the gate electrode and the element isolation region through the stopper portion serving as a stopper.
Japanese Patent Laid-Open No. 6-13606 discloses a CMOS transistor having an SOI structure with two or more silicon layers, in which a common gate whose conductivity type changes from the first conductivity type to the second conductivity type is formed, and this gate is sandwiched between silicon layers having sources/drains with gate oxide films intervened.
Japanese Patent Laid-Open No. 6-21473 discloses a technique of attaining high integration of SRAM memory cells. In this technique, a polysilicon film is deposited on an element active region including a LOCOS region (field oxide film) with a first gate oxide film intervened. The polysilicon film is polished using the LOCOS region as a stopper to planarize the polysilicon film, thereby forming a lower gate. Next, a second gate oxide film and an upper gate are sequentially formed on the planarized LOCOS region and polysilicon film.
U.S. Pat. No. 5,422,289 discloses an art in which a field oxide film is formed through LOCOS process to fix an element active region, thereafter a gate electrode with its top face planarized and leading-out wirings from the gate and source/drain are formed.
U.S. Pat. No. 5,292,683 and No. 5,397,908 disclose an art in which isolation trench formed in a semiconductor substrate is filled, thereafter an element isolation structure with its upper portion projected on the surface of the substrate is formed by chemical mechanical polishing (CMP) process.
However, the following problems are posed in gate electrode formation.
In the technique disclosed in Japanese Patent Laid-Open No. 6-21054, the first polysilicon film can hardly be left to have a predetermined thickness on the field oxide film by polishing the first polysilicon film. In addition, when the first polysilicon film is polished using the field oxide film as a stopper, and thereafter, the second polysilicon film is formed on the resultant structure, two layers of polysilicon films constituting the gate electrode are formed. Projections are generated on the surface of the first polysilicon film due to a spontaneous oxide film or a transmutative substance generated upon polishing and left between the first and second polysilicon films. In addition, this technique requires an extra polishing process to the manufacturing processes and therefore cannot meet one of important requirements associated with manufacturing of the semiconductor device, i.e., reduction of the number of processes.
Along with progresses in micropatterning and high integration of semiconductor devices, pad polysilicon films for contact extraction are formed on the source/drain of a MOS transistor to mainly modify the positional accuracy of contact holes on the source/drain of the MOS transistor. This pad polysilicon films are electrically disconnected between the source and the drain, as a matter of course, and therefore must be separated on the gate electrode.
However, when the width of the gate electrode wiring layer is reduced to the exposure limit, the resist pattern used to separate the pad polysilicon films on the gate electrode has a width equal to or smaller than the exposure limit, so the pad polysilicon films are hard to be patterned by photolithography processes. For this reason, conventionally, the width of the gate electrode wiring pattern cannot be reduced to the exposure limit, thus impeding micropatterning of a semiconductor device.
The technique disclosed in Japanese Patent Laid-Open No. 1-114041 can be used to form the mask on the polysilicon film formed on the gate electrode wiring layer and form the pad polysilicon film having a width equal to or smaller than the exposure limit on the basis of the mask pattern. However, the cumbersome processes as described above are required to form the mask. Additionally, after formation of the pad polysilicon film, the process of removing the mask is also needed. In this case, addition of the mask formation and removing processes largely increases the number of manufacturing processes, resulting in a serious problem.
The technique disclosed in Japanese Patent Laid-Open No. 8-70120 can be used to fill the polysilicon film in a self-aligned manner between the gate on the element active region and the element isolation region. Actually, the gate is formed across the element active region and the element isolation region, so this technique cannot sufficiently cope with this situation.
The technique disclosed in Japanese Patent Laid-Open No. 8-70120 can be applied to only a semiconductor device having an SOI structure and therefore cannot be used for wide application purposes. In addition, the SOI structure does not allow use of gates of the same conductivity type.
Deep problems such as development of so called bird's beak and penetration of field oxide into the element active region of the device occur in the process of the U.S. Pat. No. 5,422,289, in which an element isolation structure is constructed by a field oxide film formed by LOCOS process.
A complex step to form a sacrificial layer and then to remove-the layer can not be omitted in the process disclosed in the U.S. Pat. No. 5,292,683 and No. 5,397,908 due to structural feature of the element isolation structure.